Principal STAFF Signal Integrity Engineer (Ansys HFSS, Serdes, Cadence, Sigrity)

February 19, 2026

Principal SR STAFF Signal Integrity Engineer (Ansys HFSS, Serdes, Cadence, Sigrity) Fulltime position – 90% Remote from within the USA only. Must occasionally visit offices for onsite work in either Austin, TX or San Jose, CA. CONFIDENTIAL: Publicly traded computer HARDWARE infrastructure platform solutions company with over $5 Billion in sales whose stock price has grown over 200% in the last year because their products and services are used within Ai Data Centers. High-Speed Signal Integrity design & simulation for PCB designs with 20+ layers and speeds of 50 Gb/s or higher The Signal Integrity Design Engineering team is experiencing dramatic growth in the USA and has several newly created openings at different levels ranging from SR Engineer, Staff, SR Staff, or Principal. In general, the Signal Integrity Engineer provides design guideline and support to system architecture design, board layout, product bring up, debug, validation, and factory builds. They will also perform testing, simulation, validation and qualification of systems and makes design adjustments as needed. The Signal integrity Engineer works in cross-functional teams with other designers, customers, manufacturing engineering and project leadership to ensure robust and high-quality product development. <ul><li>Define and develop and validate Signal Integrity for next generation technologies for Networking, Server, and Storage products used in Hardware Platform Solutions for HPC – High Performance Computing and Ai Data Centers.</li><li>Models high-density I/O's on PCBs, packages, connectors and probe cards with respect to parameters such as reflections, bandwidth, and crosstalk.</li><li>Lead the design, development and implementation of technical solutions for complex Signal Integrity projects, involving multiple domains. Participate in project planning and scheduling.</li><li>Strong knowledge in simulation tools like Hspice, Sigrity, ADS, Ansys SIwave, HFSS 3D.</li><li>Strong knowledge of Signal Integrity and Power Integrity fundamental concepts.</li><li>Strong experience in Package and PCB modelling is required.</li><li>Performs Transmission line & Via modelling and carry out experiments to validate modelling outcomes and methodologies.</li><li>Should be able to analyze and review the layout files related to Signal Integrity and Power Integrity problems.</li><li>Should be able to provide practical solutions to PCB/Package design team based on simulation results and analysis.</li><li>Conducting Simulation of memory interfaces for Board and Package, and High-Speed Serial IO interfaces for Board and Package.</li></ul> REQUIREMENTS<ul><li>Must have BSEE (or similar) and 10+ years of experience with High-Speed Signal Integrity design & simulation for PCB designs with 15+ layers and speeds of 25 Gb/s or higher. (For the Principal-level role, they prefer 40+ layers and 100 Gb/s).</li><li>Should be Signal Integrity SME (Subject Matter Expert) and skilled using Ansys HFSS, Sigrity, Cadence Allegro, Keysight ADS (Advance Design Systems) for EDA (Electronic Design Automation), Ansys SIwave, Siemens Hyperlynx, Matlab.</li><li>Should have expertise in Signal Integrity, SIPI, PCIe, PAM4 – PCB Board & off board Package – Simulation & Modeling.</li><li>Should have expertise in most of the following: PCB Package/Multi-Layer Board SI and PI Modeling and Simulation.</li><li>This person must live in the USA. It is a hybrid/remote model. Mostly REMOTE, but must be willing to work onsite about once a month or as needed in Austin, TX or San Jose, CA.</li><li>Visa Sponsorship is a possibility for the right skillset.</li><li>Must have great English communication skills and ability to work with teams located around the globe. Proven ability to articulate requirements and vision to large and diverse audience through architecture specs and give verbal presentations in technical forums.</li></ul>

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